#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include <cydevice_trm.h>

/* UART_rx */
#define UART_rx__0__DM__MASK 0x7000u
#define UART_rx__0__DM__SHIFT 12
#define UART_rx__0__DR CYREG_PRT0_DR
#define UART_rx__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define UART_rx__0__HSIOM_MASK 0x000F0000u
#define UART_rx__0__HSIOM_SHIFT 16u
#define UART_rx__0__INTCFG CYREG_PRT0_INTCFG
#define UART_rx__0__INTSTAT CYREG_PRT0_INTSTAT
#define UART_rx__0__MASK 0x10u
#define UART_rx__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define UART_rx__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define UART_rx__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define UART_rx__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define UART_rx__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define UART_rx__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define UART_rx__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define UART_rx__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define UART_rx__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define UART_rx__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define UART_rx__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define UART_rx__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define UART_rx__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define UART_rx__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define UART_rx__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define UART_rx__0__PC CYREG_PRT0_PC
#define UART_rx__0__PC2 CYREG_PRT0_PC2
#define UART_rx__0__PORT 0u
#define UART_rx__0__PS CYREG_PRT0_PS
#define UART_rx__0__SHIFT 4
#define UART_rx__DR CYREG_PRT0_DR
#define UART_rx__INTCFG CYREG_PRT0_INTCFG
#define UART_rx__INTSTAT CYREG_PRT0_INTSTAT
#define UART_rx__MASK 0x10u
#define UART_rx__PA__CFG0 CYREG_UDB_PA0_CFG0
#define UART_rx__PA__CFG1 CYREG_UDB_PA0_CFG1
#define UART_rx__PA__CFG10 CYREG_UDB_PA0_CFG10
#define UART_rx__PA__CFG11 CYREG_UDB_PA0_CFG11
#define UART_rx__PA__CFG12 CYREG_UDB_PA0_CFG12
#define UART_rx__PA__CFG13 CYREG_UDB_PA0_CFG13
#define UART_rx__PA__CFG14 CYREG_UDB_PA0_CFG14
#define UART_rx__PA__CFG2 CYREG_UDB_PA0_CFG2
#define UART_rx__PA__CFG3 CYREG_UDB_PA0_CFG3
#define UART_rx__PA__CFG4 CYREG_UDB_PA0_CFG4
#define UART_rx__PA__CFG5 CYREG_UDB_PA0_CFG5
#define UART_rx__PA__CFG6 CYREG_UDB_PA0_CFG6
#define UART_rx__PA__CFG7 CYREG_UDB_PA0_CFG7
#define UART_rx__PA__CFG8 CYREG_UDB_PA0_CFG8
#define UART_rx__PA__CFG9 CYREG_UDB_PA0_CFG9
#define UART_rx__PC CYREG_PRT0_PC
#define UART_rx__PC2 CYREG_PRT0_PC2
#define UART_rx__PORT 0u
#define UART_rx__PS CYREG_PRT0_PS
#define UART_rx__SHIFT 4

/* UART_SCB */
#define UART_SCB__BIST_CONTROL CYREG_SCB1_BIST_CONTROL
#define UART_SCB__BIST_DATA CYREG_SCB1_BIST_DATA
#define UART_SCB__CTRL CYREG_SCB1_CTRL
#define UART_SCB__EZ_DATA00 CYREG_SCB1_EZ_DATA00
#define UART_SCB__EZ_DATA01 CYREG_SCB1_EZ_DATA01
#define UART_SCB__EZ_DATA02 CYREG_SCB1_EZ_DATA02
#define UART_SCB__EZ_DATA03 CYREG_SCB1_EZ_DATA03
#define UART_SCB__EZ_DATA04 CYREG_SCB1_EZ_DATA04
#define UART_SCB__EZ_DATA05 CYREG_SCB1_EZ_DATA05
#define UART_SCB__EZ_DATA06 CYREG_SCB1_EZ_DATA06
#define UART_SCB__EZ_DATA07 CYREG_SCB1_EZ_DATA07
#define UART_SCB__EZ_DATA08 CYREG_SCB1_EZ_DATA08
#define UART_SCB__EZ_DATA09 CYREG_SCB1_EZ_DATA09
#define UART_SCB__EZ_DATA10 CYREG_SCB1_EZ_DATA10
#define UART_SCB__EZ_DATA11 CYREG_SCB1_EZ_DATA11
#define UART_SCB__EZ_DATA12 CYREG_SCB1_EZ_DATA12
#define UART_SCB__EZ_DATA13 CYREG_SCB1_EZ_DATA13
#define UART_SCB__EZ_DATA14 CYREG_SCB1_EZ_DATA14
#define UART_SCB__EZ_DATA15 CYREG_SCB1_EZ_DATA15
#define UART_SCB__EZ_DATA16 CYREG_SCB1_EZ_DATA16
#define UART_SCB__EZ_DATA17 CYREG_SCB1_EZ_DATA17
#define UART_SCB__EZ_DATA18 CYREG_SCB1_EZ_DATA18
#define UART_SCB__EZ_DATA19 CYREG_SCB1_EZ_DATA19
#define UART_SCB__EZ_DATA20 CYREG_SCB1_EZ_DATA20
#define UART_SCB__EZ_DATA21 CYREG_SCB1_EZ_DATA21
#define UART_SCB__EZ_DATA22 CYREG_SCB1_EZ_DATA22
#define UART_SCB__EZ_DATA23 CYREG_SCB1_EZ_DATA23
#define UART_SCB__EZ_DATA24 CYREG_SCB1_EZ_DATA24
#define UART_SCB__EZ_DATA25 CYREG_SCB1_EZ_DATA25
#define UART_SCB__EZ_DATA26 CYREG_SCB1_EZ_DATA26
#define UART_SCB__EZ_DATA27 CYREG_SCB1_EZ_DATA27
#define UART_SCB__EZ_DATA28 CYREG_SCB1_EZ_DATA28
#define UART_SCB__EZ_DATA29 CYREG_SCB1_EZ_DATA29
#define UART_SCB__EZ_DATA30 CYREG_SCB1_EZ_DATA30
#define UART_SCB__EZ_DATA31 CYREG_SCB1_EZ_DATA31
#define UART_SCB__I2C_CFG CYREG_SCB1_I2C_CFG
#define UART_SCB__I2C_CTRL CYREG_SCB1_I2C_CTRL
#define UART_SCB__I2C_M_CMD CYREG_SCB1_I2C_M_CMD
#define UART_SCB__I2C_S_CMD CYREG_SCB1_I2C_S_CMD
#define UART_SCB__I2C_STATUS CYREG_SCB1_I2C_STATUS
#define UART_SCB__INTR_CAUSE CYREG_SCB1_INTR_CAUSE
#define UART_SCB__INTR_I2C_EC CYREG_SCB1_INTR_I2C_EC
#define UART_SCB__INTR_I2C_EC_MASK CYREG_SCB1_INTR_I2C_EC_MASK
#define UART_SCB__INTR_I2C_EC_MASKED CYREG_SCB1_INTR_I2C_EC_MASKED
#define UART_SCB__INTR_M CYREG_SCB1_INTR_M
#define UART_SCB__INTR_M_MASK CYREG_SCB1_INTR_M_MASK
#define UART_SCB__INTR_M_MASKED CYREG_SCB1_INTR_M_MASKED
#define UART_SCB__INTR_M_SET CYREG_SCB1_INTR_M_SET
#define UART_SCB__INTR_RX CYREG_SCB1_INTR_RX
#define UART_SCB__INTR_RX_MASK CYREG_SCB1_INTR_RX_MASK
#define UART_SCB__INTR_RX_MASKED CYREG_SCB1_INTR_RX_MASKED
#define UART_SCB__INTR_RX_SET CYREG_SCB1_INTR_RX_SET
#define UART_SCB__INTR_S CYREG_SCB1_INTR_S
#define UART_SCB__INTR_S_MASK CYREG_SCB1_INTR_S_MASK
#define UART_SCB__INTR_S_MASKED CYREG_SCB1_INTR_S_MASKED
#define UART_SCB__INTR_S_SET CYREG_SCB1_INTR_S_SET
#define UART_SCB__INTR_SPI_EC CYREG_SCB1_INTR_SPI_EC
#define UART_SCB__INTR_SPI_EC_MASK CYREG_SCB1_INTR_SPI_EC_MASK
#define UART_SCB__INTR_SPI_EC_MASKED CYREG_SCB1_INTR_SPI_EC_MASKED
#define UART_SCB__INTR_TX CYREG_SCB1_INTR_TX
#define UART_SCB__INTR_TX_MASK CYREG_SCB1_INTR_TX_MASK
#define UART_SCB__INTR_TX_MASKED CYREG_SCB1_INTR_TX_MASKED
#define UART_SCB__INTR_TX_SET CYREG_SCB1_INTR_TX_SET
#define UART_SCB__RX_CTRL CYREG_SCB1_RX_CTRL
#define UART_SCB__RX_FIFO_CTRL CYREG_SCB1_RX_FIFO_CTRL
#define UART_SCB__RX_FIFO_RD CYREG_SCB1_RX_FIFO_RD
#define UART_SCB__RX_FIFO_RD_SILENT CYREG_SCB1_RX_FIFO_RD_SILENT
#define UART_SCB__RX_FIFO_STATUS CYREG_SCB1_RX_FIFO_STATUS
#define UART_SCB__RX_MATCH CYREG_SCB1_RX_MATCH
#define UART_SCB__SPI_CTRL CYREG_SCB1_SPI_CTRL
#define UART_SCB__SPI_STATUS CYREG_SCB1_SPI_STATUS
#define UART_SCB__SS0_POSISTION 0u
#define UART_SCB__SS1_POSISTION 1u
#define UART_SCB__SS2_POSISTION 2u
#define UART_SCB__SS3_POSISTION 3u
#define UART_SCB__STATUS CYREG_SCB1_STATUS
#define UART_SCB__TX_CTRL CYREG_SCB1_TX_CTRL
#define UART_SCB__TX_FIFO_CTRL CYREG_SCB1_TX_FIFO_CTRL
#define UART_SCB__TX_FIFO_STATUS CYREG_SCB1_TX_FIFO_STATUS
#define UART_SCB__TX_FIFO_WR CYREG_SCB1_TX_FIFO_WR
#define UART_SCB__UART_CTRL CYREG_SCB1_UART_CTRL
#define UART_SCB__UART_RX_CTRL CYREG_SCB1_UART_RX_CTRL
#define UART_SCB__UART_RX_STATUS CYREG_SCB1_UART_RX_STATUS
#define UART_SCB__UART_TX_CTRL CYREG_SCB1_UART_TX_CTRL

/* UART_SCBCLK */
#define UART_SCBCLK__DIVIDER_MASK 0x0000FFFFu
#define UART_SCBCLK__ENABLE CYREG_CLK_DIVIDER_A00
#define UART_SCBCLK__ENABLE_MASK 0x80000000u
#define UART_SCBCLK__MASK 0x80000000u
#define UART_SCBCLK__REGISTER CYREG_CLK_DIVIDER_A00

/* UART_tx */
#define UART_tx__0__DM__MASK 0x38000u
#define UART_tx__0__DM__SHIFT 15
#define UART_tx__0__DR CYREG_PRT0_DR
#define UART_tx__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define UART_tx__0__HSIOM_MASK 0x00F00000u
#define UART_tx__0__HSIOM_SHIFT 20u
#define UART_tx__0__INTCFG CYREG_PRT0_INTCFG
#define UART_tx__0__INTSTAT CYREG_PRT0_INTSTAT
#define UART_tx__0__MASK 0x20u
#define UART_tx__0__OUT_SEL CYREG_UDB_PA0_CFG10
#define UART_tx__0__OUT_SEL_SHIFT 10u
#define UART_tx__0__OUT_SEL_VAL -1u
#define UART_tx__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define UART_tx__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define UART_tx__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define UART_tx__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define UART_tx__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define UART_tx__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define UART_tx__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define UART_tx__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define UART_tx__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define UART_tx__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define UART_tx__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define UART_tx__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define UART_tx__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define UART_tx__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define UART_tx__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define UART_tx__0__PC CYREG_PRT0_PC
#define UART_tx__0__PC2 CYREG_PRT0_PC2
#define UART_tx__0__PORT 0u
#define UART_tx__0__PS CYREG_PRT0_PS
#define UART_tx__0__SHIFT 5
#define UART_tx__DR CYREG_PRT0_DR
#define UART_tx__INTCFG CYREG_PRT0_INTCFG
#define UART_tx__INTSTAT CYREG_PRT0_INTSTAT
#define UART_tx__MASK 0x20u
#define UART_tx__PA__CFG0 CYREG_UDB_PA0_CFG0
#define UART_tx__PA__CFG1 CYREG_UDB_PA0_CFG1
#define UART_tx__PA__CFG10 CYREG_UDB_PA0_CFG10
#define UART_tx__PA__CFG11 CYREG_UDB_PA0_CFG11
#define UART_tx__PA__CFG12 CYREG_UDB_PA0_CFG12
#define UART_tx__PA__CFG13 CYREG_UDB_PA0_CFG13
#define UART_tx__PA__CFG14 CYREG_UDB_PA0_CFG14
#define UART_tx__PA__CFG2 CYREG_UDB_PA0_CFG2
#define UART_tx__PA__CFG3 CYREG_UDB_PA0_CFG3
#define UART_tx__PA__CFG4 CYREG_UDB_PA0_CFG4
#define UART_tx__PA__CFG5 CYREG_UDB_PA0_CFG5
#define UART_tx__PA__CFG6 CYREG_UDB_PA0_CFG6
#define UART_tx__PA__CFG7 CYREG_UDB_PA0_CFG7
#define UART_tx__PA__CFG8 CYREG_UDB_PA0_CFG8
#define UART_tx__PA__CFG9 CYREG_UDB_PA0_CFG9
#define UART_tx__PC CYREG_PRT0_PC
#define UART_tx__PC2 CYREG_PRT0_PC2
#define UART_tx__PORT 0u
#define UART_tx__PS CYREG_PRT0_PS
#define UART_tx__SHIFT 5

/* Pin_1 */
#define Pin_1__0__DM__MASK 0x1C0000u
#define Pin_1__0__DM__SHIFT 18
#define Pin_1__0__DR CYREG_PRT1_DR
#define Pin_1__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define Pin_1__0__HSIOM_MASK 0x0F000000u
#define Pin_1__0__HSIOM_SHIFT 24u
#define Pin_1__0__INTCFG CYREG_PRT1_INTCFG
#define Pin_1__0__INTSTAT CYREG_PRT1_INTSTAT
#define Pin_1__0__MASK 0x40u
#define Pin_1__0__OUT_SEL CYREG_UDB_PA1_CFG10
#define Pin_1__0__OUT_SEL_SHIFT 12u
#define Pin_1__0__OUT_SEL_VAL 1u
#define Pin_1__0__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Pin_1__0__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Pin_1__0__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Pin_1__0__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Pin_1__0__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Pin_1__0__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Pin_1__0__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Pin_1__0__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Pin_1__0__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Pin_1__0__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Pin_1__0__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Pin_1__0__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Pin_1__0__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Pin_1__0__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Pin_1__0__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Pin_1__0__PC CYREG_PRT1_PC
#define Pin_1__0__PC2 CYREG_PRT1_PC2
#define Pin_1__0__PORT 1u
#define Pin_1__0__PS CYREG_PRT1_PS
#define Pin_1__0__SHIFT 6
#define Pin_1__DR CYREG_PRT1_DR
#define Pin_1__INTCFG CYREG_PRT1_INTCFG
#define Pin_1__INTSTAT CYREG_PRT1_INTSTAT
#define Pin_1__MASK 0x40u
#define Pin_1__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Pin_1__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Pin_1__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Pin_1__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Pin_1__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Pin_1__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Pin_1__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Pin_1__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Pin_1__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Pin_1__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Pin_1__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Pin_1__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Pin_1__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Pin_1__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Pin_1__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Pin_1__PC CYREG_PRT1_PC
#define Pin_1__PC2 CYREG_PRT1_PC2
#define Pin_1__PORT 1u
#define Pin_1__PS CYREG_PRT1_PS
#define Pin_1__SHIFT 6

/* Pin_col */
#define Pin_col__0__DM__MASK 0x7000u
#define Pin_col__0__DM__SHIFT 12
#define Pin_col__0__DR CYREG_PRT2_DR
#define Pin_col__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_col__0__HSIOM_MASK 0x000F0000u
#define Pin_col__0__HSIOM_SHIFT 16u
#define Pin_col__0__INTCFG CYREG_PRT2_INTCFG
#define Pin_col__0__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_col__0__MASK 0x10u
#define Pin_col__0__OUT_SEL CYREG_UDB_PA2_CFG10
#define Pin_col__0__OUT_SEL_SHIFT 8u
#define Pin_col__0__OUT_SEL_VAL 1u
#define Pin_col__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_col__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_col__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_col__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_col__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_col__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_col__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_col__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_col__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_col__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_col__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_col__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_col__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_col__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_col__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_col__0__PC CYREG_PRT2_PC
#define Pin_col__0__PC2 CYREG_PRT2_PC2
#define Pin_col__0__PORT 2u
#define Pin_col__0__PS CYREG_PRT2_PS
#define Pin_col__0__SHIFT 4
#define Pin_col__1__DM__MASK 0x38000u
#define Pin_col__1__DM__SHIFT 15
#define Pin_col__1__DR CYREG_PRT2_DR
#define Pin_col__1__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_col__1__HSIOM_MASK 0x00F00000u
#define Pin_col__1__HSIOM_SHIFT 20u
#define Pin_col__1__INTCFG CYREG_PRT2_INTCFG
#define Pin_col__1__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_col__1__MASK 0x20u
#define Pin_col__1__OUT_SEL CYREG_UDB_PA2_CFG10
#define Pin_col__1__OUT_SEL_SHIFT 10u
#define Pin_col__1__OUT_SEL_VAL 3u
#define Pin_col__1__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_col__1__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_col__1__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_col__1__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_col__1__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_col__1__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_col__1__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_col__1__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_col__1__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_col__1__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_col__1__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_col__1__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_col__1__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_col__1__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_col__1__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_col__1__PC CYREG_PRT2_PC
#define Pin_col__1__PC2 CYREG_PRT2_PC2
#define Pin_col__1__PORT 2u
#define Pin_col__1__PS CYREG_PRT2_PS
#define Pin_col__1__SHIFT 5
#define Pin_col__2__DM__MASK 0x1C0000u
#define Pin_col__2__DM__SHIFT 18
#define Pin_col__2__DR CYREG_PRT2_DR
#define Pin_col__2__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_col__2__HSIOM_MASK 0x0F000000u
#define Pin_col__2__HSIOM_SHIFT 24u
#define Pin_col__2__INTCFG CYREG_PRT2_INTCFG
#define Pin_col__2__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_col__2__MASK 0x40u
#define Pin_col__2__OUT_SEL CYREG_UDB_PA2_CFG10
#define Pin_col__2__OUT_SEL_SHIFT 12u
#define Pin_col__2__OUT_SEL_VAL 2u
#define Pin_col__2__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_col__2__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_col__2__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_col__2__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_col__2__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_col__2__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_col__2__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_col__2__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_col__2__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_col__2__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_col__2__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_col__2__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_col__2__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_col__2__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_col__2__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_col__2__PC CYREG_PRT2_PC
#define Pin_col__2__PC2 CYREG_PRT2_PC2
#define Pin_col__2__PORT 2u
#define Pin_col__2__PS CYREG_PRT2_PS
#define Pin_col__2__SHIFT 6
#define Pin_col__3__DM__MASK 0xE00000u
#define Pin_col__3__DM__SHIFT 21
#define Pin_col__3__DR CYREG_PRT2_DR
#define Pin_col__3__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_col__3__HSIOM_MASK 0xF0000000u
#define Pin_col__3__HSIOM_SHIFT 28u
#define Pin_col__3__INTCFG CYREG_PRT2_INTCFG
#define Pin_col__3__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_col__3__MASK 0x80u
#define Pin_col__3__OUT_SEL CYREG_UDB_PA2_CFG10
#define Pin_col__3__OUT_SEL_SHIFT 14u
#define Pin_col__3__OUT_SEL_VAL 0u
#define Pin_col__3__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_col__3__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_col__3__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_col__3__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_col__3__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_col__3__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_col__3__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_col__3__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_col__3__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_col__3__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_col__3__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_col__3__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_col__3__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_col__3__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_col__3__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_col__3__PC CYREG_PRT2_PC
#define Pin_col__3__PC2 CYREG_PRT2_PC2
#define Pin_col__3__PORT 2u
#define Pin_col__3__PS CYREG_PRT2_PS
#define Pin_col__3__SHIFT 7
#define Pin_col__DR CYREG_PRT2_DR
#define Pin_col__INTCFG CYREG_PRT2_INTCFG
#define Pin_col__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_col__MASK 0xF0u
#define Pin_col__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_col__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_col__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_col__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_col__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_col__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_col__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_col__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_col__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_col__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_col__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_col__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_col__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_col__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_col__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_col__PC CYREG_PRT2_PC
#define Pin_col__PC2 CYREG_PRT2_PC2
#define Pin_col__PORT 2u
#define Pin_col__PS CYREG_PRT2_PS
#define Pin_col__SHIFT 4

/* Pin_row */
#define Pin_row__0__DM__MASK 0x07u
#define Pin_row__0__DM__SHIFT 0
#define Pin_row__0__DR CYREG_PRT2_DR
#define Pin_row__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_row__0__HSIOM_MASK 0x0000000Fu
#define Pin_row__0__HSIOM_SHIFT 0u
#define Pin_row__0__INTCFG CYREG_PRT2_INTCFG
#define Pin_row__0__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_row__0__MASK 0x01u
#define Pin_row__0__OUT_SEL CYREG_UDB_PA2_CFG10
#define Pin_row__0__OUT_SEL_SHIFT 0u
#define Pin_row__0__OUT_SEL_VAL 1u
#define Pin_row__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_row__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_row__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_row__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_row__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_row__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_row__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_row__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_row__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_row__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_row__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_row__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_row__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_row__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_row__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_row__0__PC CYREG_PRT2_PC
#define Pin_row__0__PC2 CYREG_PRT2_PC2
#define Pin_row__0__PORT 2u
#define Pin_row__0__PS CYREG_PRT2_PS
#define Pin_row__0__SHIFT 0
#define Pin_row__1__DM__MASK 0x38u
#define Pin_row__1__DM__SHIFT 3
#define Pin_row__1__DR CYREG_PRT2_DR
#define Pin_row__1__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_row__1__HSIOM_MASK 0x000000F0u
#define Pin_row__1__HSIOM_SHIFT 4u
#define Pin_row__1__INTCFG CYREG_PRT2_INTCFG
#define Pin_row__1__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_row__1__MASK 0x02u
#define Pin_row__1__OUT_SEL CYREG_UDB_PA2_CFG10
#define Pin_row__1__OUT_SEL_SHIFT 2u
#define Pin_row__1__OUT_SEL_VAL 0u
#define Pin_row__1__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_row__1__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_row__1__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_row__1__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_row__1__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_row__1__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_row__1__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_row__1__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_row__1__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_row__1__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_row__1__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_row__1__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_row__1__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_row__1__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_row__1__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_row__1__PC CYREG_PRT2_PC
#define Pin_row__1__PC2 CYREG_PRT2_PC2
#define Pin_row__1__PORT 2u
#define Pin_row__1__PS CYREG_PRT2_PS
#define Pin_row__1__SHIFT 1
#define Pin_row__2__DM__MASK 0x1C0u
#define Pin_row__2__DM__SHIFT 6
#define Pin_row__2__DR CYREG_PRT2_DR
#define Pin_row__2__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_row__2__HSIOM_MASK 0x00000F00u
#define Pin_row__2__HSIOM_SHIFT 8u
#define Pin_row__2__INTCFG CYREG_PRT2_INTCFG
#define Pin_row__2__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_row__2__MASK 0x04u
#define Pin_row__2__OUT_SEL CYREG_UDB_PA2_CFG10
#define Pin_row__2__OUT_SEL_SHIFT 4u
#define Pin_row__2__OUT_SEL_VAL 2u
#define Pin_row__2__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_row__2__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_row__2__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_row__2__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_row__2__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_row__2__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_row__2__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_row__2__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_row__2__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_row__2__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_row__2__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_row__2__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_row__2__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_row__2__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_row__2__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_row__2__PC CYREG_PRT2_PC
#define Pin_row__2__PC2 CYREG_PRT2_PC2
#define Pin_row__2__PORT 2u
#define Pin_row__2__PS CYREG_PRT2_PS
#define Pin_row__2__SHIFT 2
#define Pin_row__3__DM__MASK 0xE00u
#define Pin_row__3__DM__SHIFT 9
#define Pin_row__3__DR CYREG_PRT2_DR
#define Pin_row__3__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_row__3__HSIOM_MASK 0x0000F000u
#define Pin_row__3__HSIOM_SHIFT 12u
#define Pin_row__3__INTCFG CYREG_PRT2_INTCFG
#define Pin_row__3__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_row__3__MASK 0x08u
#define Pin_row__3__OUT_SEL CYREG_UDB_PA2_CFG10
#define Pin_row__3__OUT_SEL_SHIFT 6u
#define Pin_row__3__OUT_SEL_VAL 3u
#define Pin_row__3__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_row__3__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_row__3__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_row__3__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_row__3__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_row__3__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_row__3__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_row__3__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_row__3__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_row__3__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_row__3__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_row__3__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_row__3__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_row__3__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_row__3__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_row__3__PC CYREG_PRT2_PC
#define Pin_row__3__PC2 CYREG_PRT2_PC2
#define Pin_row__3__PORT 2u
#define Pin_row__3__PS CYREG_PRT2_PS
#define Pin_row__3__SHIFT 3
#define Pin_row__DR CYREG_PRT2_DR
#define Pin_row__INTCFG CYREG_PRT2_INTCFG
#define Pin_row__INTSTAT CYREG_PRT2_INTSTAT
#define Pin_row__MASK 0x0Fu
#define Pin_row__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin_row__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin_row__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin_row__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin_row__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin_row__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin_row__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin_row__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin_row__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin_row__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin_row__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin_row__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin_row__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin_row__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin_row__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin_row__PC CYREG_PRT2_PC
#define Pin_row__PC2 CYREG_PRT2_PC2
#define Pin_row__PORT 2u
#define Pin_row__PS CYREG_PRT2_PS
#define Pin_row__SHIFT 0

/* col_reg */
#define col_reg_Sync_ctrl_reg__0__MASK 0x01u
#define col_reg_Sync_ctrl_reg__0__POS 0
#define col_reg_Sync_ctrl_reg__1__MASK 0x02u
#define col_reg_Sync_ctrl_reg__1__POS 1
#define col_reg_Sync_ctrl_reg__2__MASK 0x04u
#define col_reg_Sync_ctrl_reg__2__POS 2
#define col_reg_Sync_ctrl_reg__3__MASK 0x08u
#define col_reg_Sync_ctrl_reg__3__POS 3
#define col_reg_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_UDB_W8_ACTL_03
#define col_reg_Sync_ctrl_reg__CONTROL_REG CYREG_UDB_W8_CTL_03
#define col_reg_Sync_ctrl_reg__CONTROL_ST_REG CYREG_UDB_CAT16_CTL_ST_03
#define col_reg_Sync_ctrl_reg__COUNT_REG CYREG_UDB_W8_CTL_03
#define col_reg_Sync_ctrl_reg__COUNT_ST_REG CYREG_UDB_CAT16_CTL_ST_03
#define col_reg_Sync_ctrl_reg__MASK 0x0Fu
#define col_reg_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_03
#define col_reg_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_03
#define col_reg_Sync_ctrl_reg__PERIOD_REG CYREG_UDB_W8_MSK_03

/* isr_key */
#define isr_key__INTC_CLR_EN_REG CYREG_CM0_ICER
#define isr_key__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define isr_key__INTC_MASK 0x01u
#define isr_key__INTC_NUMBER 0u
#define isr_key__INTC_PRIOR_MASK 0xC0u
#define isr_key__INTC_PRIOR_NUM 3u
#define isr_key__INTC_PRIOR_REG CYREG_CM0_IPR0
#define isr_key__INTC_SET_EN_REG CYREG_CM0_ISER
#define isr_key__INTC_SET_PD_REG CYREG_CM0_ISPR

/* row_reg */
#define row_reg_Sync_ctrl_reg__0__MASK 0x01u
#define row_reg_Sync_ctrl_reg__0__POS 0
#define row_reg_Sync_ctrl_reg__1__MASK 0x02u
#define row_reg_Sync_ctrl_reg__1__POS 1
#define row_reg_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_UDB_W16_ACTL_02
#define row_reg_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_UDB_W16_CTL_02
#define row_reg_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_UDB_W16_CTL_02
#define row_reg_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_UDB_W16_CTL_02
#define row_reg_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_UDB_W16_CTL_02
#define row_reg_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_UDB_W16_MSK_02
#define row_reg_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_UDB_W16_MSK_02
#define row_reg_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_UDB_W16_MSK_02
#define row_reg_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_UDB_W16_MSK_02
#define row_reg_Sync_ctrl_reg__2__MASK 0x04u
#define row_reg_Sync_ctrl_reg__2__POS 2
#define row_reg_Sync_ctrl_reg__3__MASK 0x08u
#define row_reg_Sync_ctrl_reg__3__POS 3
#define row_reg_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_UDB_W8_ACTL_02
#define row_reg_Sync_ctrl_reg__CONTROL_REG CYREG_UDB_W8_CTL_02
#define row_reg_Sync_ctrl_reg__CONTROL_ST_REG CYREG_UDB_CAT16_CTL_ST_02
#define row_reg_Sync_ctrl_reg__COUNT_REG CYREG_UDB_W8_CTL_02
#define row_reg_Sync_ctrl_reg__COUNT_ST_REG CYREG_UDB_CAT16_CTL_ST_02
#define row_reg_Sync_ctrl_reg__MASK 0x0Fu
#define row_reg_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define row_reg_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define row_reg_Sync_ctrl_reg__PERIOD_REG CYREG_UDB_W8_MSK_02

/* isr_uart */
#define isr_uart__INTC_CLR_EN_REG CYREG_CM0_ICER
#define isr_uart__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define isr_uart__INTC_MASK 0x800u
#define isr_uart__INTC_NUMBER 11u
#define isr_uart__INTC_PRIOR_MASK 0xC0000000u
#define isr_uart__INTC_PRIOR_NUM 3u
#define isr_uart__INTC_PRIOR_REG CYREG_CM0_IPR2
#define isr_uart__INTC_SET_EN_REG CYREG_CM0_ISER
#define isr_uart__INTC_SET_PD_REG CYREG_CM0_ISPR

/* GlitchFilter_1 */
#define GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_A0_REG CYREG_UDB_W16_A0_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_A1_REG CYREG_UDB_W16_A1_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_D0_REG CYREG_UDB_W16_D0_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_D1_REG CYREG_UDB_W16_D1_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_DP_AUX_CTL_REG CYREG_UDB_W16_ACTL_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_F0_REG CYREG_UDB_W16_F0_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_F1_REG CYREG_UDB_W16_F1_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__A0_A1_REG CYREG_UDB_CAT16_A_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__A0_REG CYREG_UDB_W8_A0_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__A1_REG CYREG_UDB_W8_A1_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__D0_D1_REG CYREG_UDB_CAT16_D_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__D0_REG CYREG_UDB_W8_D0_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__D1_REG CYREG_UDB_W8_D1_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__DP_AUX_CTL_REG CYREG_UDB_W8_ACTL_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__F0_F1_REG CYREG_UDB_CAT16_F_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__F0_REG CYREG_UDB_W8_F0_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__F1_REG CYREG_UDB_W8_F1_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__MSK_DP_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define GlitchFilter_1_genblk2_Counter0_DP_u0__PER_DP_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02

/* Miscellaneous */
#define CY_VERSION "PSoC Creator  3.1 SP1"
#define CYDEV_BCLK__HFCLK__HZ 24000000U
#define CYDEV_BCLK__HFCLK__KHZ 24000U
#define CYDEV_BCLK__HFCLK__MHZ 24U
#define CYDEV_BCLK__SYSCLK__HZ 24000000U
#define CYDEV_BCLK__SYSCLK__KHZ 24000U
#define CYDEV_BCLK__SYSCLK__MHZ 24U
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PANTHER 6u
#define CYDEV_CHIP_DIE_PSOC4A 3u
#define CYDEV_CHIP_DIE_PSOC5LP 5u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
#define CYDEV_CHIP_JTAG_ID 0x04C81193u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 3u
#define CYDEV_CHIP_MEMBER_4D 2u
#define CYDEV_CHIP_MEMBER_4F 4u
#define CYDEV_CHIP_MEMBER_5A 6u
#define CYDEV_CHIP_MEMBER_5B 5u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4A
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4A_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_READ_ACCELERATOR 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_PROTECT_KILL 4
#define CYDEV_DEBUG_PROTECT_OPEN 1
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_STACK_SIZE 0x0400
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 1
#define CYDEV_VDDA 3.3
#define CYDEV_VDDA_MV 3300
#define CYDEV_VDDD 3.3
#define CYDEV_VDDD_MV 3300
#define CYIPBLOCK_M0S8_CTBM_VERSION 0
#define CYIPBLOCK_m0s8cpuss_VERSION 0
#define CYIPBLOCK_m0s8csd_VERSION 0
#define CYIPBLOCK_m0s8gpio2_VERSION 0
#define CYIPBLOCK_m0s8hsiom4a_VERSION 0
#define CYIPBLOCK_m0s8lcd_VERSION 0
#define CYIPBLOCK_m0s8lpcomp_VERSION 0
#define CYIPBLOCK_m0s8pclk_VERSION 0
#define CYIPBLOCK_m0s8sar_VERSION 0
#define CYIPBLOCK_m0s8scb_VERSION 0
#define CYIPBLOCK_m0s8srssv2_VERSION 1
#define CYIPBLOCK_m0s8tcpwm_VERSION 0
#define CYIPBLOCK_m0s8udbif_VERSION 0
#define CYIPBLOCK_S8_GPIO_VERSION 2
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
